<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>ARM Cortex-M4 on Vamsi Kiran | Firmware Engineer</title><link>https://vamsikiran277.github.io/tags/arm-cortex-m4/</link><description>Recent content in ARM Cortex-M4 on Vamsi Kiran | Firmware Engineer</description><generator>Hugo</generator><language>en-us</language><lastBuildDate>Sun, 12 Apr 2026 10:00:00 +0000</lastBuildDate><atom:link href="https://vamsikiran277.github.io/tags/arm-cortex-m4/index.xml" rel="self" type="application/rss+xml"/><item><title>STM32F4 Bare-Metal LED Toggle (Bit-Field &amp; SIL)</title><link>https://vamsikiran277.github.io/projects/bitfield-optimization/</link><pubDate>Sun, 12 Apr 2026 10:00:00 +0000</pubDate><guid>https://vamsikiran277.github.io/projects/bitfield-optimization/</guid><description>&lt;h3 id="-technology-stack"&gt;🛠 Technology Stack&lt;/h3&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Language:&lt;/strong&gt; C (C11/C17)&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Hardware:&lt;/strong&gt; STM32F407 (ARM Cortex-M4)&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Tools:&lt;/strong&gt; Renode (SIL Simulation), STM32CubeIDE&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Key Concepts:&lt;/strong&gt; C Bit-Fields, MMIO, Software-in-the-Loop (SIL)&lt;/li&gt;
&lt;/ul&gt;
&lt;hr&gt;
&lt;h3 id="the-project-overview"&gt;The Project Overview&lt;/h3&gt;
&lt;p&gt;A low-level firmware implementation for the STM32F407 that demonstrates peripheral control via direct register manipulation. This project bypasses standard HAL/LL libraries to interface directly with the &lt;strong&gt;AHB1 bus matrix&lt;/strong&gt; using custom C bit-field structures for type-safe hardware access.&lt;/p&gt;
&lt;h3 id="technical-highlights"&gt;Technical Highlights&lt;/h3&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;C Bit-Field Structures:&lt;/strong&gt; Utilized custom &lt;code&gt;struct&lt;/code&gt; definitions to map hardware registers, ensuring type-safe access to individual bits and eliminating manual bitwise masks (&lt;code&gt;&amp;amp;&lt;/code&gt;, &lt;code&gt;|&lt;/code&gt;, &lt;code&gt;&amp;lt;&amp;lt;&lt;/code&gt;).&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Memory-Mapped I/O (MMIO):&lt;/strong&gt; Manually mapped the RCC (Base: &lt;code&gt;0x40023800&lt;/code&gt;) and GPIOD (Base: &lt;code&gt;0x40020C00&lt;/code&gt;) to control hardware clocking and pin states.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;SIL Validation (Renode):&lt;/strong&gt; Automated hardware verification using Renode to validate register-level behavior via memory-access tracing. This allows for cycle-accurate auditing of the firmware&amp;rsquo;s execution without physical hardware.&lt;/li&gt;
&lt;/ul&gt;
&lt;h3 id="-simulation--hardware-verification"&gt;🔍 Simulation &amp;amp; Hardware Verification&lt;/h3&gt;
&lt;p&gt;The project is validated using &lt;strong&gt;Renode&lt;/strong&gt; to trace memory-mapped I/O (MMIO) interactions. This ensures the firmware logic correctly targets the ARM Cortex-M4 register map before deployment to physical silicon.&lt;/p&gt;</description></item></channel></rss>